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[ak4103a] ms0251-e-01 2009/01 - 1 - general description the ak4103a is a digital audio transmitter (dit) whic h supports data rate up to 192khz sample rate operation. the ak4103a supports aes3, iec60958, s/pdif & eiaj cp1201 interface standards. the ak4103a accepts audio data, auxilia ry information data and etc, which is then biphase-encoded and driven on to a cable. the audio seri al port supports eight formats. features ? sampling rate up to 192khz ? support aes3, iec60958, s/pdif & eiaj cp1201 professional and consumer formats ? generates crcc codes and parity bits ? on-chip rs422 line driver ? 16-byte on-chip buffer memory fo r channel status and user bits ? supports synchronous/asynchronous access to channel status and user bits ? supports multiple clock frequencies: 128fs, 256fs, 384fs and 512fs ? supports left/right justified and i 2 s audio formats ? easy to use 4 wire, serial host interface ? audio routing mode (transparent mode) ? power supply: 4.75 to 5.25v ? ttl level i/f ? small package: 24pin vsop ? temperature range of - 40 to 85 c 192khz 24-bit dit ak4103a
[ak4103a] ms0251-e-01 2009/01 - 2 - block diagram host serial interface audio serial interface bick lrck sdti txp mux crcc generator prescaler rs422 line driver biphase encoder dif2 dif1 dif0 cks1 cks0 mclk bls trans vss vdd txn c1 u1 v1 fs0 fs1 fs2 fs3 register csn ccl k cdti cdto ans pdn
[ak4103a] ms0251-e-01 2009/01 - 3 - ordering guide AK4103AVF -40 +85 c 24pin vsop (0.65mm pitch) akd4103a evaluation board for ak4103a pin layout 6 5 4 3 2 1 v1 trans mclk pdn sdti bick lrck 7 fs0/csn 8 u1 dif2 dif1 dif0 txp txn vss vdd top view 10 9 fs1/cdti fs2/cclk fs3/cdto 11 c1 12 cks1 cks0 bls a ns 19 20 21 22 23 24 18 17 15 16 14 13 comparison ak4103 with ak4103a function ak4103 ak4103a ambient temperature -10 ~ 70 c -40 ~ 85 c crcc generation by fs3-0 pi ns synchronous mode x o crcc generation by fs3-0 bits asynchronous mode x o o: input data is reflected to crcc. x: input data is ignored for crcc.
[ak4103a] ms0251-e-01 2009/01 - 4 - pin/function no. pin name i/o description 1 v1 i validity bit input pin 2 trans i audio routing mode (transpa rent mode) pin at synchronous mode 0: normal mode, 1: audio routing mode (transparent mode) 3 pdn i power down & reset pin (pull-up pin) when ?l?, the ak4103a is powered-down, txp/n pins are ?l? and the control registers are reset to default values. 4 mclk i master clock input pin 5 sdti i audio serial data input pin 6 bick i/o audio serial data clock input/output pin serial clock for sdti pin which can be configured as an output based on the dif2-0 inputs. 7 lrck i/o input/output channel clock pin indicates left or right channel, and can be configured as an output based on the dif2-0 inputs. fs0 i sampling frequency select 0 pin at synchronous mode (pull-down pin) csn i host interface chip select pin at asynchronous mode (pull-down pin) 8 akmode i ak4112b mode pin at audio routing mode (pull-down pin) 0: non-akm receive rs mode, 1: ak4112b mode fs1 i sampling frequency select 1 pin at synchronous mode (pull-down pin) 9 cdti i host interface data input pin at asynchronous mode (pull-down pin) fs2 i sampling frequency select 2 pin at synchronous mode (pull-down pin) 10 cclk i host interface bit clock input pin at asynchronous mode (pull-down pin) fs3 i sampling frequency select 3 pin at synchronous mode (pull-down pin) 11 cdto o host interface data output pin at asynchronous mode (pull-down pin) 12 c1 i channel status bit input pin 13 ans i asynchronous/synchronous mode select pin (pull-up pin) 0: asynchronous mode, 1: synchronous mode 14 bls i/o block start input/output pin (pull-down pin) in normal mode, the channel status block output is ?h? for the first four bytes. in audio routing mode, the pin is configured as an input. when pdn pin = ?l?, bls pin goes ?h? at normal mode. 15 cks0 i clock mode select 0 pin (pull-up pin) 16 cks1 i clock mode select 1 pin (pull-down pin) 17 vdd - power supply pin, 4.75v 5.25v 18 vss - ground pin, 0v 19 txn o negative diffe rential output pin 20 txp o positive differential output pin 21 dif0 i audio serial interface select 0 pin (pull-down pin) 22 dif1 i audio serial interface select 1 pin (pull-down pin) 23 dif2 i audio serial interface select 2 pin (pull-down pin) 24 u1 i user data bit input pin for channel 1 (pull-down pin) note 1. internal pull-up and pull-down resistors are connected on-chip. the value of the resistors is 43k (typ). note 2. all input pins except internal pull-down/pull-up pins should not be left floating.
[ak4103a] ms0251-e-01 2009/01 - 5 - absolute maximum ratings (vss=0v; note 3 ) parameter symbol min max units power supply vdd -0.3 6.0 v input current (all pins except supply pins) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note 3. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss=0v; note 3) parameter symbol min typ max units power supply vdd 4.75 5.0 5.25 v *akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. dc characteristics (ta=25 c; vdd=4.75~5.25v) parameter symbol min typ max units power supply current (fs=108khz, note 4 ) idd 6 15 ma high-level input voltage low-level input voltage vih vil 2.4 - - - - 0.8 v v high-level output voltage (except txp/n pins: iout=-400a) (txp/n pins: iout= -8ma) low-level output voltage (except txp/n pins: iout= 400a) (txp/n pins: iout= 8ma) voh voh vol vol vdd-1.0 vdd-0.8 - - - - - - - - 0.4 0.6 v v v v input leakage current iin - - 10 a note 4. power supply current (idd) is 3ma(typ)@fs=48khz and 9ma(typ)@fs=192khz. idd increases by 20ma(typ) with professional output driver circuit. idd is 350 a(typ) if pdn pin = ?l?, trans pin = ?h? and all other input pins except internal pull-up/pull- down pins are held to vss.
[ak4103a] ms0251-e-01 2009/01 - 6 - switching characteristics (ta=25 c; vdd=4.75~5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency duty cycle fclk dclk 3.584 40 27.648 60 mhz % lrck timing frequency duty cycle at slave mode duty cycle at master mode fs dlck 28 45 50 192 55 khz % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 5) bick ? ? to lrck edge ( note 5) sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tsdh tsds 36 15 15 15 15 8 8 ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck sdti hold time sdti setup time fbck dbck tmblr tsdh tsds -20 20 20 64fs 50 20 hz % ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z ( note 6) tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 520 50 50 45 70 ns ns ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width tpdw 150 ns note 5. bick rising edge must not occur at the same time as lrck edge. note 6. cdto pin is internally connected to a pull-down resistor.
[ak4103a] ms0251-e-01 2009/01 - 7 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk = tclkh x fclk x 100 = tclkl x fclk x 100 vih lrck vil 1/fs tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio interface timing (slave mode) lrck bick tmblr 50%vdd 50%vdd sdti tsdh tsds vih vil audio interface timing (master mode)
[ak4103a] ms0251-e-01 2009/01 - 8 - tcckl csn cclk tcds cdti tcdh tcss c0 * tcckh cdto hi-z (with pull-down resistor) * c1 vih vil vih vil vih vil write/read command input timing tcsw csn cclk cdti d2 d0 tcsh cdto d1 d3 vih vil vih vil vih vil hi-z (with pull-down resistor) write data input timing csn cclk tdcd cdto cdti a1 a0 hi-z (with pull-down resistor) 50%vdd vih vil vih vil vih vil d7 d6 d5 read data output timing 1
[ak4103a] ms0251-e-01 2009/01 - 9 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%vdd vih vil vih vil vih vil read data output timing 2 tpdw pdn vil power-down & reset timing
[ak4103a] ms0251-e-01 2009/01 - 10 - operation overview general description the ak4103a is a monolithic cmos circu it that biphase-encodes and transmits a udio data, auxiliary information data and etc according to the aes3, iec60958, s/pdif and eiaj cp1201 interface standa rds. there is one set of stereo channels that can be transmitted simulta neously. the chip accepts audio data and auxiliary information data separately, biphase-mark encodes the data internally, and drives it directly or through a transformer to a transmission line. there are two modes of operation: asynchronous and synchronous. see section of ?asynchronous mode / synchronous mode?. initialization the ak4103a takes 8 bit clock cycles to initialize after p dn pin goes inactive. also, fo r correct synchronization, mclk should be synchronized with l rck but the phase is not critical. mclk and lrck relationship for correct synchronization, mclk and lrck should be de rived from the same clock signal either directly (as through a frequency divider) or indirectly (for example, as th rough a dsp). the relationship of bick to lrck is fixed and should not change. if mclk or lrck move such that they are shifted (128fs x 3) or more mclk cycles from their initial conditions, the chip will reset the internal frame and bit count ers. however, control registers are not initialized. the following frequencies are supported for mclk. cks1 cks0 mclk fs 0 0 128fs 28k-192khz 0 1 256fs 28k-108khz 1 0 384fs 28k-54khz 1 1 512fs 28k-54khz table 1. mclk frequency asynchronous mode/ synchronous mode 1. asynchronous mode (software controlled) the ak4103a can be configured in the asynchronous mode by connecting the ans pin to logic ?l?. in this mode the 16 to 24-bit audio samples are accepted through a configured a udio serial port, and the cha nnel status and user data through a serial control host interface (sci). the sci allows access to internal buffer me mory and control registers which are used to store the channel status and user data. 4by tes per channel of user and channel status is stored. this data is multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is biphase-mark encoded and driven through the rs422 line dr iver. the crcc code for the channel status is also generated according to the professional m ode definition in the aes3 standards. this mode also allows for software control for mute, reset, audio format se lection, clock frequency setti ngs and output enables, via the serial host interface.
[ak4103a] ms0251-e-01 2009/01 - 11 - 2. synchronous mode (hardware controlled) the ak4103a when configured in synchronous mode accepts 16 - 24 bit audio samples th rough the audio serial port and provides dedicated pins for the control data and allows all channel status, user data and validity bits to be serially input through port pins. this data is multip lexed, the parity bit generated, and the bit stream is biphase-mark encoded and driven through an rs422 line driver. 2-1. audio routing mode (transparent mode) the ak4103a can be configured in audio routing mode (tra nsparent mode) by ans pin = trans pin = ?h?. in this mode, the channel status(c), user data(u) and validity(v) b its must pass through unaltered. the block start(b) signal is configured as an input, allowing the transm it block structure to be slaved to the block structure of the receiver. the c, u and v are now transmitted with the current audio sample. in audio routing mode, no crcc bytes are generated and c bits pass through unaltered. in audio routing mode, the fs0/csn pin changes definiti on to akmode pin. when set ?h? the ak4103a can be configured dir ectly with the ak4112b receiver. when set ?l?, it may be used with other non-akm receivers. setting the part with trans pin = ?h? and ans pin = ?l? is illegal and places the chip into a test mode. pin modes ans trans synchronous/asynchronous audio routing source for c, u and v bits l l asynchronous mode normal mode c pin ored control register u pin ored control register v pin ored control register l h (test mode) h l normal mode h h synchronous mode audio routing mode c,u and v pin table 2. mode setting bls c (or u,v) c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) sdti lrck (i 2 s) l0 r0 l31 r31 r191 l1 l32 lrck (except i 2 s) figure 1. audio routing mode timing (akmode pin = ?0?)
[ak4103a] ms0251-e-01 2009/01 - 12 - bls c (or u,v) lrck c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) sdti (except i 2 s) l191 r191 l0 r30 r31 l31 sdti (i 2 s) l191 r191 l30 l31 r30 l0 r190 r0 figure 2. audio routing mode timing (akmode pin = ?1?) block start timing normal mode in normal mode (trans pin = ?l?), the block start signal is an output. it goes ?h? two bit cycle after the beginning of channel 2 of frame 0 in each block, and stays ?h? for the first 32 frames. audio routing mode (transparent mode) in audio routing mode (transparent mode) (ans pin = trans pin = ?h?), the block start becomes an input. except in i 2 s mode, a block start signal sampled any time from the first positive bick edge of the previous left channel to the positive bick edge preceding the transiti on of an lrck indicating the left ch annel will result in the current left channel being taken as the first sub frame of the current block. see figure 3 below. bick lrck (except i 2 s) (n-1)th channel 1 nth channel 1 lrck (i 2 s) (n-1)th channel 1 nth channel 1 (1) figure 3. block start timing in audio routing mode a block start signal arriving during ?(1)? period will result in the usage of ?nth channel 1? as the first sub-frame of the block.
[ak4103a] ms0251-e-01 2009/01 - 13 - c, u, v serial ports normal mode in normal mode (trans pin = ?l?), the c, u and v bits are captured (either from the pins, in synchronous mode, or the control registers, in the asynchronous mode) in the sub frame following the audio data. the v bit is set to zero to indicate the audio data is suitable for conversion. see figure 4 and figure 5 . audio routing mode (transparent mode) in audio routing mode (transparent mode) (ans pin = trans pin = ?h?), the c, u and v bits are captured with the same sub-frame as the data to which the c, u and v bits correspond. in all dif modes except 5 and 7, the c, u and v bits are captured at the first, rising edge of bick after an lrck transition. in modes 5 and 7 (i 2 s), the c, u and v bits are captured at the second rising edge. see figure 6 and figure 7 . c,u,v bick lrck channel1 channel 2 channel 1 c,u, v previous channel 2 c, u, v figure 4. normal, dif modes 0/1/2/3/4/6 c,u,v bick lrck channel 1 channel 2 channel 1 c, u, v previous channel 2 c, u, v figure 5. normal, dif modes 5 and 7 (i 2 s) c,u,v bick lrck channel 1 c, u, v channel 1 channel 2 channel 2 c, u, v figure 6. audio routing, dif modes 0/1/2/3/4/6
[ak4103a] ms0251-e-01 2009/01 - 14 - c,u,v bick lrck channel 1 c, u, v channel 1 channel 2 channel 2 c, u, v figure 7. audio routing, dif modes 5 and 7 (i 2 s) audio serial interface the audio serial interface is used to i nput audio data and consists of three pi ns: bit clock (bick), word clock (lrck) & data pin (sdti). lrck indicates the particular channel, left or right. the dif 2-0 pins in synchronous mode and control registers in asynchronous mode select the partic ular input mode. in asynchronous mode, dif2-0 bits are logically ored with dif2-0 pins. audio data format supports 16-24 bits, right justified and left justified modes. the i 2 s mode is also supported. the ak4103a can be configured in master and slave modes. mode dif2 dif1 dif0 sdti master / slave lrck bick 0 0 0 0 16bit, right justified slave h/l (i) 32fs-128fs (i) 1 0 0 1 18bit, right justified slave h/l (i) 36fs-128fs (i) 2 0 1 0 20bit, right justified slave h/l (i) 40fs-128fs (i) 3 0 1 1 24bit, right justified slave h/l (i) 48fs-128fs (i) 4 1 0 0 24bit, left justified slave h/l (i) 48fs-128fs (i) 5 1 0 1 24bit, i 2 s slave l/h (i) 50fs-128fs (i) 6 1 1 0 24bit, left justified master h/l (o) 64fs (o) 7 1 1 1 24bit, i 2 s master l/h (o) 64fs (o) table 3. audio data format modes [note; (i): input, (o): output] lrck(i) bick(i) sdti(i) 012 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 010 1 30 15 14 14 15 30 figure 8. mode 0 timing
[ak4103a] ms0251-e-01 2009/01 - 15 - lrck(i) bick(i) sdti(i) 0 1 2 31 0 1 17:msb, 0:lsb lch data rch data 13 15 14 13 31 0 1 2 15 14 01 0 1 30 17 16 16 17 30 figure 9. mode 1 timing lrck(i) bick(i) sdti(i) 0 1 2 31 0 1 19:msb, 0:lsb lch data rch data 11 13 12 11 31 0 1 2 13 12 01 0 1 30 19 18 18 19 30 figure 10. mode 2 timing lrck(i) bick(i) sdti(i) 01 8 31 0 1 23:msb, 0:lsb lch data rch data 911 10 9 31 0 1 8 11 10 010 1 30 21 20 20 21 30 22 23 22 23 figure 11. mode 3 timing
[ak4103a] ms0251-e-01 2009/01 - 16 - lrck bick sdti(i) 012 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 30 1 0 0 1 30 21 22 23 21 2 23 22 figure 12. mode 4/6 timing mode 4: lrck, bick: input mode 6: lrck, bick: output lrck bick sdti(i) 012 31 0 1 23:msb, 0:lsb lch data rch data 23 32 31 0 1 23 3 23 22 24 1 0 24 32 23 22 2 0 1 21 22 23 22 figure 13. mode 5/7 timing mode 5: lrck, bick: input mode 7: lrck, bick: output
[ak4103a] ms0251-e-01 2009/01 - 17 - sampling frequency setting bits 3-0 of channel status byte 3 in consumer mode can be set by fs3-0 pins. also bits 7-6 of channel status byte 0 and bits 6-3 of channel status byte 4 in professional mode can be set by fs3-0 pins. fs[3:0] sampling frequency byte 3 bits 3-0 0000 44.1khz 0000 0001 not indicated 0001 0010 48khz 0010 0011 32khz 0011 0100 22.05khz 0100 0101 reserved 0101 0110 24khz 0110 0111 reserved 0111 1000 88.2khz 1000 1001 reserved 1001 1010 96khz 1010 1011 reserved 1011 1100 176.4khz 1100 1101 reserved 1101 1110 192khz 1110 1111 reserved 1111 table 4. sampling frequency setting (consumer mode) fs[3:0] sampling frequency byte 0 bits 7-6 byte 4 bits 6-3 0000 not defined 00 0000 0001 44.1khz 01 0000 0010 48khz 10 0000 0011 32khz 11 0000 0100 not defined 00 0000 0101 not defined 00 0000 0110 not defined 00 0000 0111 not defined 00 0000 1000 for vectoring 00 1000 1001 22.05khz 00 1001 1010 88.2khz 00 1010 1011 176.4khz 00 1011 1100 192khz 00 0011 1101 24khz 00 0001 1110 96khz 00 0010 1111 not defined 00 1111 table 5. sampling frequency setting (professional mode)
[ak4103a] ms0251-e-01 2009/01 - 18 - data transmission format data transmitted on the tx outputs is formatted in blocks as shown in figure 14 . each block consists of 192 frames. a frame of data contains two sub-frames. a sub-frame consists of 32 bits of inform ation. each data bit received is coded using a bi-phase mark encoding as a two binary state symbol . the preambles violate bi-phase encoding so they may be differentiated from data. in bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. for a logic ?0?, the second state of the symbol is the same as the first state. for a ?1?, the second state is the opposite of the first. figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states. frame 191 frame 0 frame 1 sub-frame sub-frame m channel 1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 figure 14. block format 0 1 1 0 0 0 1 0 figure 15. a biphase-encoded bit stream the sub-frame is defined in figure 16 below. bits 0-3 of the sub-frame repr esent a preamble for synchronization. there are three preambles. the block preamble, b, is contained in the first sub-frame of frame 0. the channel 1 preamble, m, is contained in the first sub-frame of all other frames. the channel 2 preamble, w, is contained in all of the second sub- frames. table 6 below defines the symbol encoding for each of the preambles. bits 4-27 of the sub-frame contain the 24 bit audio sample in 2?s complement format with bit 27 as the most significant bit. for 16 bit mode, bits 4-11 are all 0. bit 28 is the validity flag. this is ?h? if the audio sample is unre liable. bit 29 is a user data bit. frame 0 contains the first bit of a 192 bit user data word. frame 191 contains the last bit of the user data word. bit 30 is a channel status bit. again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. bit 31 is an even parity bit for bits 4-31 of the sub-frame. sync p c u v l m s audio sample s b b 0 3 4 27 28 29 30 31 figure 16. sub-frame format the block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. for stereophonic audio, the left or a channel data is in channe l 1 while the right or b data is in channel 2. for monophonic audio, channel 1 contains the audio data. preamble preceding state = 0 preceding state = 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 table 6. sub-frame preamble encoding
[ak4103a] ms0251-e-01 2009/01 - 19 - line driver there is an rs422 line driver on chip. the aes3 specification states that the line driver shall have a balanced output with an internal impedance of 110 ohms 20% and also requires a balanced output drive capability of 2 to 7 volts peak- to-peak into 110 ohm load. the internal impedance of the rs422 driver along with a series resistors of 56 ohms realizes this requirement. for consumer use(s/pdif), the sp ecifications require an output impedance of 75 ohms 20% and a driver level of 0.5 20% volts peak to peak. a combination of 330 ohms in parallel with 100 ohms realizes this requirement. the outputs can be set to ground by resetting the device or a software mute. txp txn 56 0.1u xlr connector transformer figure 17. professional output driver circuit txp txn 330 0.1u rca phono connector transformer 100 figure 18. consumer output driver circuit
[ak4103a] ms0251-e-01 2009/01 - 20 - serial control interface in asynchronous mode, four of the dual function pins become csn, cclk, cdti and cdto, a 4 wire microprocessor interface. the internal 18 byte control regi ster can then be read and written. the c ontents of the contro l register define, in part, the mode of operation for the ak4103a. figure 19 illustrates the serial data flow associated with sci read and write operations. c1-0 bits are the chip address. the ak4103a looks for c1-0 bits to be a ?11? before responding to the incoming data. r/w is the read/ write bit which is ?0? for a read operation and ?1? for a write operation. the register address contained in a7-0 bits is decoded to select a particular byte of the control register. d7-0 bits on cdti pin is the control data coming from the microprocessor during a write operation. d7-0 bits on cdto pin is the contents of the addressed byte from the control register requested dur ing a read operation. the address and data bits are framed by csn pin = ?0?. during a write operati on, each address and data bit is sample d on the rising edge of cclk. during a read operation, the address bits are sampled on the rising edge of cclk while data on cdto is output on the falling edge of cclk. cclk has a maximum frequency of 5 mhz. cdti cclk csn c1 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 d4 d5 d6 d7 * * * * * c0 r/w d0 d1 d2 d3 cdto hi-z (with pull-down resistor) write cdti c1 d4 d5 d6 d7 * * * * * c0 r/w d0 d1 d2 d3 cdto hi-z (with pull-down resistor) read d4 d5 d6 d7 d0 d1 d2 d3 hi-z a7 8 9 101112131415 a1 a2 a3 a4 a5 a6 a0 a7 a1 a2 a3 a4 a5 a6 a0 ?l? c1-c0: chip address (fixed to ?11?) r/w: read/write (0:read, 1:write) *: don?t care a7-a0: register address d7-d0: control data figure 19. control i/f timing csn ak4103a cclk cdti cdto csn ak4103a cclk cdti cdto p csn1 cclk cdti cdto csn2 figure 20. typical connection with p note: external pull-up resistor should not be attached to cdto pins since cdto pin is internally connected to the pull-down resistor.
[ak4103a] ms0251-e-01 2009/01 - 21 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock/format control crce dif2 dif1 dif0 cks1 cks0 muten rstn 01h validity/fs control 0 0 0 v1 fs3 fs2 fs1 fs0 02h a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 03h a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 04h a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 05h a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 06h- 09h b-channel c-bit buffer for byte 0-3 cb7 ? cb31 ? ? ? ? ? ? ? ? ? ? ? ? cb0 ? cb24 0ah- 0dh a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 0eh- 11h b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 table 7. register map notes: (1) in stereo mode, a indicates left channel and b indicates right channel. (2) in asynchronous mode, the dif2-0 and cks1-0 bits are logically ?ored? with the dif2-0 and cks1-0 pins. (3) for addresses from 12h to ffh, data is not written. (4) the pdn pin = ?l? resets the re gisters to their default values.
[ak4103a] ms0251-e-01 2009/01 - 22 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock/format control crce dif2 dif1 dif0 cks1 cks0 muten rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 1 1 rstn: timing reset. 0: resets the internal frame and bit count ers. control registers are not initialized. txp pin is ?h? and txn pin is ?l?. in normal mode, bls pin is ?h?. 1: normal operation. (default) muten: power down and mute for asynchronous mode. 0: power down command. control registers are not initialized. txp and txn pins are ?l?. in normal mode, bls pin is ?h?. 1: normal operation. (default) cks1-0: master clock frequency select. ( table 1 ) default: ?00? (mode 0: mclk=128fs) cks1-0 bits are logically ored with cks1-0 pins. dif2-0: audio data format. ( table 3 ) default: ?000? (mode 0: 16bit right justified) dif2-0 bits are logically ored with dif2-0 pins. crce: crcc enable at professional mode. 0: crcc is not generated. 1: crcc is generated at professional mode. in consumer mode, crcc is not generated. (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h validity/fs control 0 0 0 v1 fs3 fs2 fs1 fs0 r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency select. ( table 4 and table 5 ) default: ?0000? (?44.1khz? in consumer mode; ?not defined? in professional mode. ) v1: validity flag. 0: valid (default) 1: invalid
[ak4103a] ms0251-e-01 2009/01 - 23 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 06h b-channel c-bit buffer for byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 1 0 0 c0-7: channel status byte 0 default: ?00100000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 07h b-channel c-bit buffer for byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 c8-15: channel status byte 1 default: ?00000000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ca16-23: channel status byte 2 for a-channel default: ?00001000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h b-channel c-bit buffer for byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 0 cb16-23: channel status byte 2 for b-channel default: ?00000100? addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 09h b-channel c-bit buffer for byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 c24-31: channel status byte 3 default: ?01000000?
[ak4103a] ms0251-e-01 2009/01 - 24 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah- 0dh a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 0eh- 11h b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 u0-31: user data default: all ?0? default values of control registers bits default crce 1 crcc is generated. dif2-0 000 16bit, right justified cks1-0 00 mclk=128fs v1 0 valid data fs3-0 0000 fs=44.1khz muten 1 normal operation rstn 1 normal operation channel status - bit0 0 consumer mode - bit1 0 audio mode - bit2 1 no copyright - bit3-5 000 no emphasis byte0 - bit6-7 00 mode 0 byte1 - bit0-7 00000000 general category code - bit0-3 0000 source number: don?t care byte2 - bit4-7 1000 0100 channel a source channel channel b source channel - bit0-3 0100 fs=48khz - bit4-5 00 standard clock accuracy byte3 - bit6-7 00 user data all zeros table 8. default values of control register
[ak4103a] ms0251-e-01 2009/01 - 25 - package 0.1 0.1 0-1 0 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15 0.05 0.65 *7. 8 0.1 5 1.25 0.2 a 1 12 13 24 2 4 p in vsop ( unit: mm ) 7. 6 0.2 0.5 0.2 *5.6 0. 2 0.22 +0.1 0 ?0. 0 5 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder plate (pb free)
[ak4103a] ms0251-e-01 2009/01 - 26 - marking a km a k4103avf a axxx x contents of aaxxxx aa: lot# xxxx: date code revision history date (yy/mm/dd) revision reason page contents 03/07/28 00 first edition 09/01/09 01 specification change 25 package the pin width dimension was changed.
[ak4103a] ms0251-e-01 2009/01 - 27 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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